Enhanced technology mapping for FPGAs with exploration of cell configurations. (c2011)

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dc.contributor.author Zgheib, Grace Joseph
dc.date.accessioned 2011-11-04T08:31:36Z
dc.date.available 2011-11-04T08:31:36Z
dc.date.copyright 2011 en_US
dc.date.issued 2011-11-04
dc.date.submitted 2011-08-02
dc.identifier.uri http://hdl.handle.net/10725/963
dc.description Includes bibliographical references (leaves 53-55). en_US
dc.description.abstract In the state of the art Field-Programmable Gate Arrays (FPGAs), logic circuits are synthesized and mapped on clusters of look-up tables. However, when additions need to be performed, an adder along with a carry-chain is used to ensure a fast execution of such an arithmetic operation. This carry-chain is a dedicated wire available in the architecture of the FPGA and is as such independent of the external programmable routing resources. The proposed idea introduces variable-structure Boolean matching as well as decomposition of mapped functions in order to take advantage of the carry-chains when they are not used for addition operations. Previously synthesized and mapped logic functions are adapted so that their outputs are routed using the dedicated carry-chains instead of the external programmable interconnects. Mapping onto these chains yields a reduction in the overall external routing resources as well as the general routing congestion. Moreover, a generic software platform was developed allowing users to identify and test various basic-unit structures and compare their performances on particular logic circuits depending on criteria specified by the user. Such structures may vary from currently available FPGA architectures to customized theoretical structures well-suited for a specific design(s). This tool can also propose particular cell structures to map logic circuits while respecting the user's constraints and insuring the optimization of specific parameters. en_US
dc.language.iso en en_US
dc.subject Field programmable gate arrays en_US
dc.subject Programmable logic devices -- Design and construction en_US
dc.subject Logic circuits -- Design and construction en_US
dc.subject Data mining en_US
dc.title Enhanced technology mapping for FPGAs with exploration of cell configurations. (c2011) en_US
dc.type Thesis en_US
dc.term.submitted Summer I en_US
dc.author.school Engineering en_US
dc.author.idnumber 200401077 en_US
dc.author.commembers Zahi Nakad en_US
dc.author.commembers Wissam Fawaz en_US
dc.author.woa OA en_US
dc.author.department MSE in Computer Engineering en_US
dc.description.physdesc 1 bound copy: xii, 98 leaves; ill.; 30 cm. available at RNL. en_US
dc.author.division Computer Engineering en_US
dc.author.advisor lyad Ouaiss en_US
dc.keywords Field Programmable Gate Array en_US
dc.keywords Technology Mapping en_US
dc.keywords Boolean Matching en_US
dc.keywords Decomposition en_US
dc.keywords Carry Chain en_US
dc.keywords Cell Configuration en_US
dc.identifier.doi https://doi.org/10.26756/th.2011.16 en_US

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