Abstract:
In the state of the art Field-Programmable Gate Arrays (FPGAs), logic circuits are
synthesized and mapped on clusters of look-up tables. However, when additions need to be
performed, an adder along with a carry-chain is used to ensure a fast execution of such an
arithmetic operation. This carry-chain is a dedicated wire available in the architecture of the
FPGA and is as such independent of the external programmable routing resources.
The proposed idea introduces variable-structure Boolean matching as well as
decomposition of mapped functions in order to take advantage of the carry-chains when
they are not used for addition operations. Previously synthesized and mapped logic
functions are adapted so that their outputs are routed using the dedicated carry-chains
instead of the external programmable interconnects. Mapping onto these chains yields a
reduction in the overall external routing resources as well as the general routing congestion.
Moreover, a generic software platform was developed allowing users to identify and test
various basic-unit structures and compare their performances on particular logic circuits
depending on criteria specified by the user. Such structures may vary from currently
available FPGA architectures to customized theoretical structures well-suited for a specific
design(s). This tool can also propose particular cell structures to map logic circuits while
respecting the user's constraints and insuring the optimization of specific parameters.
