Methods for system-on-chip test design, scheduling and optimization. (c2006)

Abstract

In this thesis we tackle three problems related to System-on-Chip. The first problem deals with test pattern generation. The purpose is to generate a set of test patterns that catch all the faults in a core. The problem is solved using a dynamic ants based algorithm. The second problem, deals with test scheduling for System-on-chip. The problem was to test the cores of the SOC with minimum time, given a fixed allocated TAM and a given power consumption for every core, and the following constraints, the instantaneous TAM width and power consumption has a total maximum limit, the core are also ruled by precedence and concurrency constraints. In this thesis we adapt a session less scheme to minimize idle slots. Finally, the third problem that we solve is defined in a similar way to the second problem, but with the difference that the allocated TAM width for each core is not fixed and should be calculated efficiently. The last two problems are solved using the simulated annealing technique. We present experimental results to compare our work to other previous ones.