Abstract:
One of the major enhancements that can be made to the synthesis process is reducing the
overall area of a design in order to either decrease the manufacturing costs or introduce
more functionality to the design. Optimizing the area of the data path is considered a
primary field of research in High-Level Synthesis (HLS). This work proposes an
approach to reduce the area by simultaneously tackling the three central tasks of HLS.
Scheduling, allocation and binding are performed and the optimal solution based on area
reduction is obtained by using simulated annealing with a priority function. The aim of
the priority function is to guide the simulated annealing process into finding the best
solution while at the same time incurring the least possible execution time. In order to
achieve better results than the initial solution, rescheduling, swapping operations
between functional units, swapping variables between registers and swapping inputs to
functional units are considered in the annealing process. A cost function was devised to
evaluate a potential move's success or failure. The simulation environment ttEridanustt
was developed in order to support implementation and testing. Several benchmarks were
tested and the numerical results consisting of the execution time along with the best
solution were recorded to illustrate the performance of the proposed technique. Area
reduction was obtained compared to the conventional HLS flow; furthermore, n average
substantial reduction in design space exploration time was obtained compared to nonpriority
based area optimization techniques.
