Multigrid solvers in reconfigurable hardware. (c2006)

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dc.contributor.author Kasbah, Safaa J.
dc.date.accessioned 2011-10-21T10:14:59Z
dc.date.available 2011-10-21T10:14:59Z
dc.date.copyright 2006 en_US
dc.date.issued 2011-10-21
dc.date.submitted 2006-06-28
dc.identifier.uri http://hdl.handle.net/10725/849
dc.description Bibliography: leaves 78-93. en_US
dc.description.abstract Physical, chemical and biological phenomena are modeled using Partial Differential Equations (PDEs). Interpreting and solving PDEs is the key for understanding the behavior of the modeled system. The broad field of modeling real systems has drawn the researchers' attention for designing efficient algorithms for solving PDEs. The Multigrid method has been shown to be the fastest method due to its high convergence rate regardless of the problem size. However, the computation of such solvers is complex and time consuming. Many attempts for exploiting the inherent parallelism of Multigrid have been made to achieve the desired efficiency and scalability of the method. Yet, most efforts fail in this respect due to many factors (time and resources) governed by software implementations upon parallelizing the algorithm. Reconfigurable Computing (RC), a new computing paradigm which combines the flexibility of software and the performance of hardware, is best suited for such computational intensive applications. In this thesis, we present a hardware implementation of the V-cycle MG algorithm for the solution of a 2D Poisson Equation using different classes of Field Programmable Gate Arrays (FPGAs). We use Handel-C, a high-level design language for hardware development, to code our design which is synthesized, and placed & routed using the FPGAs proprietary software. Our design has been tested using the Handel-C simulator; afterwards, we have targeted a Xilinx Virtex II Pro FPGA, Altera Stratix FPGA and the RCI 0 board from Celoxica. The performance of MG on hardware has been compared with the performance of a software version, written in C++, and running on a General Purpose Processor. Final results demonstrate that running the V -cycle MG on an FPGA exploits the inherent parallelism of the algorithm yielding an algorithm which outperforms a software version. en_US
dc.language.iso en en_US
dc.subject Differential equations, Partial -- Numerical solutions en_US
dc.subject Field programmable gate arrays en_US
dc.subject Multigrid methods (Numerical analysis) en_US
dc.title Multigrid solvers in reconfigurable hardware. (c2006) en_US
dc.type Thesis en_US
dc.term.submitted Spring en_US
dc.author.degree MS in Computer Science en_US
dc.author.school Arts and Sciences en_US
dc.author.idnumber 200100650 en_US
dc.author.commembers Dr. Faisal Abu Khzam
dc.author.commembers Dr. May Abboud
dc.author.commembers Dr. Issam Damaj
dc.author.woa OA en_US
dc.description.physdesc 1 bound copy: xiv, 93 leaves; ill. (some col.); 30 cm. Available at RNL. en_US
dc.author.division Computer Science en_US
dc.author.advisor Dr. Ramzi A. Haraty
dc.identifier.doi https://doi.org/10.26756/th.2006.46 en_US
dc.publisher.institution Lebanese American University en_US

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