Resource allocation and reallocation techniques in high-level synthesis with testability constraint

Abstract

The increase in density that the advent of Very Large Scale Integration (VLSI) has allowed, made the move to higher levels of design abstraction imperative. High Level Synthesis emerged as a result; however, most solutions (1) were not optimal; (2) did not incorporate testing at the system level. In this Work, we propose a prototype high-level synthesis system with self-testability, SYNTEST, that alleviates the above problems. SYNTEST is based on a model that treats testing as a structural design property during data path allocation. Thus, the design is testable by construction and there is no need for the traditional post-design test insertion methods. The most significant aspect of this work is that it covers the void between the fields of high-level synthesis and design for testability. This allows to exploit the tight relation that exists between both disciplines in an integrated system level design environment. The allocation method incorporates a test points (registers) selection method which trades test overhead for fault coverage. We follow the allocation method with a reallocation method which aims at exploring any possible design improvements which may be due to the non-optimal nature of the design process. By considering placement and routing, in addition to compon ent cost, the reallocation modifications become more effective and more realistic. Another motivation for the reallocation process is that it may be desirable to reuse the old data path in order to generate an alternate structure under a different technology. Thus, the designer may reuse the old structure to generate a new one, optimized under a different cost function. The reallocation phase is based on a rip-and-rebind approach. Finally, we automatically generate VHDL output from SYNTEST in order to complete the silicon compilation iteration. The output is a mixed behavioral and structural VHDL description of a testable data path and a controller. We link SYNTEST to the COMPASS Design Automation tools, through VHDL, which serves as our means to validate our design model and architecture. We validate our approach using various design and benchmark examples and several chips layouts were generated.