A multiobjective optimization method for the SOC Test Time, TAM, and power optimization using a strength pareto evolutionary algorithm

Abstract

System-On-Chip (SOCs) test minimization is an important problem that has been receiving considerable attention. The problem is tightly coupled with the number of TAM bits, power, and wrapper design. This paper presents a multiobjective optimization approach for the SOC test scheduling problem. The method uses a Strength Pareto Evolutionary Algorithm that minimizes the overall test application time in addition to power, wrapper design and TAM assignment. We present various experimental results that demonstrate the effectiveness of our method.