Synthesis with VHDL. (c2001)

Abstract

The need of high-level behavioral languages that make it easier to programmers to design hardware raised the issue of high-level synthesis. High-level synthesis is concerned with the design and implementation of circuits from behavioral description of some high-level languages that contain a set of goals and constraints. Synthesis is defined as the translation of a behavioral description into a structural one. Doing this requires a synthesis tool that helps to get a good and efficient output design from a behavioral description. A synthesis tool that takes a behavioral description and outputs a schedule is presented in this thesis. The synthesis tool is made of many two main components that also made of smaller ones. The first component is the translator that translates a behavioral code into an intermediate form that will be the input of the second component. The second component is the scheduler. The scheduler takes objects (nodes) and schedules them using some scheduling algorithms that are presented in the thesis.