Concurrent bist cost estimation during data path allocation. (c2003)

Abstract

The increase in density that the advent of Very Large Scale Integration (VLSI) has allowed made the move to higher levels of design abstraction imperative. High Level Synthesis emerged as a result; however, most solutions 1) were not optimal; 2) did not incorporate testing at the system level. Recently, a new trend in high-level synthesis has emerged, with researches being aware of the importance of testability at the system level. In this work we introduce a method for concurrent BIST cost estimation during testable data path allocation. A basic feature of this method is the integration of testability in the design process. The main objective is to develop a system-level synthesis tool set mapping a behavioral description onto an optimized and testable RTL design subject to user-defined constraints. The method considers test points cost concurrently with design cost. In order to measure the performance of our method, we use six data flow graphs which are widely adopted for benchmarking high-level BIST synthesis.