Global memory mapping for FPGA-based reconfigurable systems

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dc.contributor.author Ouaiss, Iyad
dc.contributor.author Vemiri, Ranga
dc.date.accessioned 2017-12-01T12:03:38Z
dc.date.available 2017-12-01T12:03:38Z
dc.date.copyright 2001 en_US
dc.date.issued 2017-12-01
dc.identifier.uri http://hdl.handle.net/10725/6692
dc.description.abstract Synthesizing designs for FPGA-based reconfigurable systems involves the task of mapping variables and data structures of the application onto RAMs of the reconfigurable board. The variety in types and performance of onboard and on-chip RAMs, their proximity to the processing units, and the interconnection scheme of the reconfigurable system, all contribute to an intricate memory mapping problem. An intelligent memory assignment minimizes the total latency of the design and the interconnection requirements due to memory accesses. A complete Integer Linear Programming (ILP) formulation of the problem results in an optimized memory mapping; however, the formulation is complex and takes a very long time to produce a solution. In order to efficiently solve the problem, the concept of global/detailed memory mapping is introduced in this paper. An ILP formulation of the global mapping process is described. This formulation is simpler and faster than the complete formulation, and it leaves the task of detailed mapping to a post-ILP tool that does not affect the optimality of the memory assignment. As a result, larger designs can be handled at a faster rate and more constraints can be introduced to the formulation en_US
dc.language.iso en en_US
dc.title Global memory mapping for FPGA-based reconfigurable systems en_US
dc.type Conference Paper / Proceeding en_US
dc.author.school SOE en_US
dc.author.idnumber 200105659 en_US
dc.author.department Electrical And Computer Engineering en_US
dc.description.embargo N/A en_US
dc.identifier.ctation Ouaiss, I., & Vemuri, R. (2001, April). Global memory mapping for FPGA-based reconfigurable systems. In null (p. 30144b). IEEE. en_US
dc.author.email iyad.ouaiss@lau.edu.lb en_US
dc.identifier.tou http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php en_US
dc.identifier.url https://www.researchgate.net/profile/Iyad_Ouaiss/publication/220950099_Global_memory_mapping_for_FPGA-based_reconfigurable_systems/links/0046352ee00bea81db000000.pdf en_US
dc.author.affiliation Lebanese American University en_US

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