A unified specification model of concurrency and coordination for synthesis from VHDL

Abstract

This paper proposes a Unified Specification Model (USM) of concurrency and coordination compatible with VHDL. The specification model embodies a uniform treatment of computation, communication channels, and memories, facilitating its use across a variety of synthesis applications. We briefly discuss synthesis semantics of the USM representation and its use in behavioral VLSI synthesis, co-synthesis, and adaptive system synthesis. We also discuss the advantages of the synchronization model in USM in comparison to similar VHDL motivated representations. Keywords: Input Specification Model, Behavioral HighLevel Synthesis, Hardware/Software Co-synthesis, Adaptive System Synthesis, and VHDL. 1. INTRODUCTION VHDL has been used for behavior level specifications for a variety of high-level synthesis tools, hardwaresoftware co-synthesis systems, and adaptive system synthesis environments. VHDL provides a rich set of high-level constructs to permit succinct specification of concurrent and coor...