dc.contributor.author |
Ouaiss, I. |
|
dc.contributor.author |
Govindarajan, S. |
|
dc.contributor.author |
Srinivasan, V. |
|
dc.contributor.author |
Kaul, M. |
|
dc.contributor.author |
Vemuri, R. |
|
dc.date.accessioned |
2017-06-22T10:07:44Z |
|
dc.date.available |
2017-06-22T10:07:44Z |
|
dc.date.issued |
2017-06-22 |
|
dc.identifier.isbn |
0-8186-8900-5 |
en_US |
dc.identifier.uri |
http://hdl.handle.net/10725/5814 |
|
dc.description.abstract |
Abstract:
The SPARCS system is an integrated partitioning and synthesis environment for reconfigurable architectures. In this paper, we use the Joint Photographic Experts Group (JPEG) image compression algorithm as a design example to demonstrate the effectiveness of dynamic reconfiguration achieved using SPARCS. We present a typical design process using the SPARCS system consisting of temporal partitioning, spatial partitioning, and design synthesis. The results, obtained on a commercial RC architecture, show that the multiply-reconfigured version of the JPEG compression algorithm achieves reasonable improvement in execution times compared to the one-time configured version. |
en_US |
dc.language.iso |
en |
en_US |
dc.publisher |
IEEE |
en_US |
dc.title |
An effective design system for dynamically reconfigurable architectures |
en_US |
dc.type |
Conference Paper / Proceeding |
en_US |
dc.author.school |
SOE |
en_US |
dc.author.idnumber |
200105659 |
en_US |
dc.author.department |
Electrical And Computer Engineering |
en_US |
dc.description.embargo |
N/A |
en_US |
dc.keywords |
Reconfigurable architectures |
en_US |
dc.keywords |
Algorithm design and analysis |
en_US |
dc.keywords |
Partitioning algorithms |
en_US |
dc.keywords |
Computer architecture |
en_US |
dc.keywords |
Transform coding |
en_US |
dc.keywords |
Discrete cosine transforms |
en_US |
dc.keywords |
Field programmable gate arrays |
en_US |
dc.keywords |
Image coding |
en_US |
dc.keywords |
Process design |
en_US |
dc.keywords |
Compression algorithms |
en_US |
dc.identifier.doi |
http://dx.doi.org/10.1109/FPGA.1998.707932 |
en_US |
dc.identifier.ctation |
Govindarajan, S., Ouaiss, I., Kaul, M., Srinivasan, V., & Vemuri, R. (1998, April). An effective design system for dynamically reconfigurable architectures. In FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on (pp. 312-313). IEEE. |
en_US |
dc.author.email |
iyad.ouaiss@lau.edu.lb |
en_US |
dc.conference.date |
17 April 1998 |
en_US |
dc.conference.place |
Napa Valley, CA, USA |
en_US |
dc.conference.title |
IEEE Symposium on FPGAs for Custom Computing Machines, 1998 |
en_US |
dc.identifier.tou |
http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php |
en_US |
dc.identifier.url |
http://ieeexplore.ieee.org/abstract/document/707932/ |
en_US |
dc.author.affiliation |
Lebanese American University |
en_US |