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An integrated partitioning and synthesis system for dynamically reconfigurable Multi-FPGA architectures

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dc.contributor.author Ouaiss, Iyad
dc.contributor.author Govindarajan, Sriram
dc.contributor.author Srinivasan, Vinoo
dc.contributor.author Kaul, Meenakshi
dc.contributor.author Vemuri, Ranga
dc.date.accessioned 2017-06-22T09:32:48Z
dc.date.available 2017-06-22T09:32:48Z
dc.identifier.uri http://hdl.handle.net/10725/5812
dc.description.abstract This paper presents an integrated design system called SPARCS (Synthesis and Partitioning for Adaptive Reconfigurable Computing Systems) for automatically partitioning and synthesizing designs for reconfigurable boards with multiple field-programmable devices (FPGAS). The SPARCS system accepts design specifications at the behavior level, in the form of task graphs. The system contains a temporal partitioning tool to temporally divide and schedule the tasks on the reconfigurable architecture, a spatial partitioning tool to map the tasks to individual FPGAs, and a high-level synthesis tool to synthesize efficient register-transfer level designs for each set of tasks destined to be downloaded on each FPGA. Commercial logic and layout synthesis tools are used to complete logic synthesis, placement, and routing for each FPGA design segment. A distinguishing feature of the SPARCS system is the tight integration of the partitioning and synthesis tools to accurately predict and control design performance and resource utilizations. This paper presents an overview of SPARCS and the various algorithms used in the system, along with a brief description of how a JPEG-like image compression algorithm is mapped to a Multi-FPGA board using SPARCS. en_US
dc.language.iso en en_US
dc.publisher Springer en_US
dc.title An integrated partitioning and synthesis system for dynamically reconfigurable Multi-FPGA architectures en_US
dc.type Conference Paper / Proceeding en_US
dc.author.school SOE en_US
dc.author.idnumber 200105659 en_US
dc.author.department Electrical And Computer Engineering en_US
dc.description.embargo N/A en_US
dc.identifier.doi http://dx.doi.org/10.1007/3-540-64359-1_669 en_US
dc.identifier.ctation Ouaiss, I., Govindarajan, S., Srinivasan, V., Kaul, M., & Vemuri, R. (1998, March). An integrated partitioning and synthesis system for dynamically reconfigurable multi-FPGA architectures. In International Parallel Processing Symposium (pp. 31-36). Springer Berlin Heidelberg. en_US
dc.author.email iyad.ouaiss@lau.edu.lb en_US
dc.conference.date March 30 – April 3, 1998 en_US
dc.conference.pages 31-36 en_US
dc.conference.place Orlando, FL, USA en_US
dc.conference.title International Parallel Processing Symposium en_US
dc.identifier.tou http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php en_US
dc.identifier.url https://link.springer.com/chapter/10.1007/3-540-64359-1_669 en_US
dc.author.affiliation Lebanese American University en_US
dc.relation.numberofseries 1388 en_US
dc.title.volume Parallel and Distributed Processing en_US


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