Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers

Ouaiss, I.; Vemuri, R.

dc.contributor.author	Ouaiss, I.
dc.contributor.author	Vemuri, R.
dc.date.accessioned	2017-06-21T10:23:03Z
dc.date.available	2017-06-21T10:23:03Z
dc.date.issued	2017-06-21
dc.identifier.isbn	0-7695-0993-2	en_US
dc.identifier.uri	http://hdl.handle.net/10725/5808
dc.language.iso	en	en_US
dc.publisher	ACM	en_US
dc.title	Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers	en_US
dc.type	Conference Paper / Proceeding	en_US
dc.author.school	SOE	en_US
dc.author.idnumber	200105659	en_US
dc.author.department	Electrical And Computer Engineering	en_US
dc.description.embargo	N/A	en_US
dc.identifier.ctation	Ouaiss, I., & Vemuri, R. (2001, March). Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers. In Proceedings of the conference on Design, automation and test in Europe (pp. 650-657). IEEE Press.	en_US
dc.author.email	iyad.ouaiss@lau.edu.lb	en_US
dc.conference.pages	650-657	en_US
dc.conference.place	Munich, Germany	en_US
dc.conference.title	Proceedings of the conference on Design, automation and test in Europe	en_US
dc.identifier.tou	http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php	en_US
dc.identifier.url	http://dl.acm.org/citation.cfm?id=367841	en_US
dc.author.affiliation	Lebanese American University	en_US