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Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers

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Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers

Ouaiss, I.; Vemuri, R.
URI: http://hdl.handle.net/10725/5808
URL: http://dl.acm.org/citation.cfm?id=367841
Date: 2017-06-21
Terms of Use: This item is made available under the terms and conditions applicable to " Conference Paper / Proceeding ", as set forth at: http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php

Citation:

Ouaiss, I., & Vemuri, R. (2001, March). Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers. In Proceedings of the conference on Design, automation and test in Europe (pp. 650-657). IEEE Press.

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