Storage allocation for diverse FPGA memory specifications

Abstract

A previous study [1] demonstrates the advantages of replacing registers by FPGA embedded memories during the storage allocation phase of High-Level Synthesis. The trend in new FPGAs to have large amounts of on-chip embedded memories motivated this proposition and resulted in substantial area decrease in the synthesized designs. This paper elaborates further on the various possibilities involved during storage allocation onto embedded memories, and presents new memory binding techniques. These techniques include modifications to the memory mapping procedure presented in [1] and cater to various memory specifications. The embedded memories differ in their assumptions of the number of memory banks, the number of ports on each bank, and the read/write types of each port. The paper highlights the benefits of the new techniques and discusses the pros and cons involved in each case. The Discrete Cosine Transform (DCT) benchmark illustrates the area improvements obtained in the new approaches compared to conventional register binding (up to 47%). The results are evaluated through an analysis of both area and delay performances.