Storage allocation for diverse FPGA memory specifications

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dc.contributor.author Ouaiss, Iyad
dc.contributor.author Dagher, Dalia
dc.date.accessioned 2017-06-21T10:09:16Z
dc.date.available 2017-06-21T10:09:16Z
dc.date.issued 2017-06-21
dc.identifier.uri http://hdl.handle.net/10725/5806
dc.description.abstract A previous study [1] demonstrates the advantages of replacing registers by FPGA embedded memories during the storage allocation phase of High-Level Synthesis. The trend in new FPGAs to have large amounts of on-chip embedded memories motivated this proposition and resulted in substantial area decrease in the synthesized designs. This paper elaborates further on the various possibilities involved during storage allocation onto embedded memories, and presents new memory binding techniques. These techniques include modifications to the memory mapping procedure presented in [1] and cater to various memory specifications. The embedded memories differ in their assumptions of the number of memory banks, the number of ports on each bank, and the read/write types of each port. The paper highlights the benefits of the new techniques and discusses the pros and cons involved in each case. The Discrete Cosine Transform (DCT) benchmark illustrates the area improvements obtained in the new approaches compared to conventional register binding (up to 47%). The results are evaluated through an analysis of both area and delay performances. en_US
dc.language.iso en en_US
dc.publisher Springer en_US
dc.title Storage allocation for diverse FPGA memory specifications en_US
dc.type Conference Paper / Proceeding en_US
dc.author.school SOE en_US
dc.author.idnumber 200105659 en_US
dc.author.department Electrical And Computer Engineering en_US
dc.description.embargo N/A en_US
dc.identifier.doi http://dx.doi.org/10.1007/978-3-540-30117-2_62 en_US
dc.identifier.ctation Dagher, D., & Ouaiss, I. (2004). Storage allocation for diverse FPGA memory specifications. Field Programmable Logic and Application, 606-616. en_US
dc.author.email iyad.ouaiss@lau.edu.lb en_US
dc.conference.date August 30-September 1, 2004 en_US
dc.conference.pages 606-616 en_US
dc.conference.place Berlin, Heidelberg en_US
dc.conference.title International Conference on Field Programmable Logic and Applications en_US
dc.identifier.tou http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php en_US
dc.identifier.url https://link.springer.com/chapter/10.1007/978-3-540-30117-2_62 en_US
dc.author.affiliation Lebanese American University en_US
dc.relation.numberofseries 3203 en_US
dc.title.volume Field Programmable Logic and Application en_US

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