Optimizing register binding in FPGAs using simulated annealing

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dc.contributor.author Ouaiss, I.
dc.date.accessioned 2017-06-21T09:53:44Z
dc.date.available 2017-06-21T09:53:44Z
dc.date.issued 2017-06-21
dc.identifier.isbn 0-7695-2456-7 en_US
dc.identifier.uri http://hdl.handle.net/10725/5805
dc.description.abstract When variables are assigned to registers or memories in FPGAs, multiplexers are needed for correct operation of the design. These multiplexers are needed at the input registers or memories if different functional units are writing to the same storage unit. Since in FPGAs the area covered by multiplexers is significantly large compared with the area of the overall design, reducing the area of the multiplexers can reduce the overall area occupied by a design. Reducing the area of a design is essential to efficiently utilize the logic area of the FPGAs. This paper proposes a solution that applies simulated annealing after binding variables to storage elements. This solution optimizes the assignment of variables onto registers when standard techniques such as clique partitioning are used; and onto on-chip memory banks when two different memory binding techniques are used. The savings obtained in terms of multiplexer area reaches 27% with an average of 16%; moreover, the overall logic area savings reaches 17% with an average of 7% en_US
dc.language.iso en en_US
dc.publisher IEEE en_US
dc.title Optimizing register binding in FPGAs using simulated annealing en_US
dc.type Conference Paper / Proceeding en_US
dc.author.school SOE en_US
dc.author.idnumber 200105659 en_US
dc.author.department Electrical And Computer Engineering en_US
dc.description.embargo N/A en_US
dc.keywords Field programmable gate arrays en_US
dc.keywords Simulated annealing en_US
dc.keywords Multiplexing en_US
dc.keywords Registers en_US
dc.keywords Design engineering en_US
dc.keywords Algorithm design and analysis en_US
dc.keywords Computational modeling en_US
dc.keywords Writing en_US
dc.keywords Logic design en_US
dc.keywords Programmable logic arrays en_US
dc.identifier.doi http://dx.doi.org/10.1109/RECONFIG.2005.27 en_US
dc.identifier.ctation Avakian, A., & Ouaiss, I. (2005, September). Optimizing register binding in FPGAs using simulated annealing. In Reconfigurable Computing and FPGAs, 2005. ReConFig 2005. International Conference on (pp. 8-pp). IEEE. en_US
dc.author.email iyad.ouaiss@lau.edu.lb en_US
dc.conference.date 28-30 Sept. 2005 en_US
dc.conference.place Puebla City, Mexico en_US
dc.conference.title International Conference on Reconfigurable Computing and FPGAs en_US
dc.identifier.tou http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php en_US
dc.identifier.url http://ieeexplore.ieee.org/abstract/document/1592498/ en_US
dc.author.affiliation Lebanese American University en_US

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