SYNTEST

Harmanani, H.; Papchristou, C.; Chiu, S.

SYNTEST

Harmanani, H.; Papchristou, C.; Chiu, S.

URI: http://hdl.handle.net/10725/5466

URL: http://ieeexplore.ieee.org/abstract/document/139947/

DOI: http://dx.doi.org/10.1109/ICCD.1991.139947

Date: 2017-03-30

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Abstract:

The article introduces a new high-level synthesis method for self-testable RTL designs. A basic feature of this method is a structural testability model which treats testability as a structural design style integrated in the design process. The main objective is to develop a system-level synthesis tool set mapping a behavioral description onto an optimized and testable RTL design subject to user-defined constraints. The approach involves several major components within the following system-level iteration: scheduling and allocation, constraint estimation, and testability tradeoffs.

Citation:

Papachristou, C., Chiu, S., & Harmanani, H. (1991, October). SYNTEST: a method for high-level SYNthesis with self-TESTability. In Computer Design: VLSI in Computers and Processors, 1991. ICCD'91. Proceedings, 1991 IEEE International Conference on (pp. 458-462). IEEE.