An evolutionary approach for data path synthesis

Harmanani, H.M.; Saliba, R.

An evolutionary approach for data path synthesis

Harmanani, H.M.; Saliba, R.

URI: http://hdl.handle.net/10725/5463

URL: http://ieeexplore.ieee.org/abstract/document/849734/

DOI: http://dx.doi.org/10.1109/CCECE.2000.849734

Date: 2017-03-30

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Abstract:

This paper presents an evolutionary approach to solve the data path allocation problem in high-level synthesis. From a behavioral description and a set of constraints, the method generates a VHDL RTL data path and a controller structure with a minimal cost. The proposed method was implemented using the C language on a Linux workstation. We tested our method on various high-level synthesis benchmarks, all yielding good solutions in a short time. Designs were validated using Altera Max+Plus II.

Citation:

Harmanani, H. M., & Saliba, R. (2000). An evolutionary approach for data path synthesis. In Electrical and Computer Engineering, 2000 Canadian Conference on (Vol. 1, pp. 380-384). IEEE.