| dc.contributor.author | Harmanani, H. | |
| dc.contributor.author | Karablieh, B. | |
| dc.date.accessioned | 2017-03-30T08:48:11Z | |
| dc.date.available | 2017-03-30T08:48:11Z | |
| dc.date.issued | 2017-03-30 | |
| dc.identifier.isbn | 0-7695-2403-6 | en_US |
| dc.identifier.uri | http://hdl.handle.net/10725/5460 | |
| dc.description.abstract | Test generation is a highly complex and time-consuming task. In this work, we present a distributed method for combinational test generation. The method is based on a hybrid approach that combines both deterministic and genetic approaches. The deterministic phase is based on the D-algorithm and generates an initial set of test vectors that are evolved in the genetic phase in order to achieve high fault coverage in a short time. The algorithm is parallelized based on a cluster of workstations using the message passing interface (MPI) library. Several benchmark circuits were attempted, and favorable results comparisons are reported | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | IEEE | en_US |
| dc.title | A hybrid distributed test generation method using deterministic and genetic algorithms | en_US |
| dc.type | Conference Paper / Proceeding | en_US |
| dc.author.school | SAS | en_US |
| dc.author.idnumber | 199490170 | en_US |
| dc.author.department | Computer Science and Mathematics | en_US |
| dc.description.embargo | N/A | en_US |
| dc.keywords | Hybrid power systems | en_US |
| dc.keywords | Genetic algorithms | en_US |
| dc.keywords | Circuit testing | en_US |
| dc.keywords | Circuit faults | en_US |
| dc.keywords | Automatic test pattern generation | en_US |
| dc.keywords | Circuit simulation | en_US |
| dc.keywords | Partitioning algorithms | en_US |
| dc.keywords | Computational modeling | en_US |
| dc.keywords | Computer science | en_US |
| dc.keywords | Mathematics | en_US |
| dc.identifier.doi | http://dx.doi.org/10.1109/IWSOC.2005.13 | en_US |
| dc.identifier.ctation | Harmanani, H., & Karablieh, B. (2005, July). A hybrid distributed test generation method using deterministic and genetic algorithms. In System-on-Chip for Real-Time Applications, 2005. Proceedings. Fifth International Workshop on (pp. 317-322). IEEE. | en_US |
| dc.author.email | haidar.harmanani@lau.edu.lb | en_US |
| dc.conference.date | 20-24 July 2005 | en_US |
| dc.conference.pages | 317-322 | en_US |
| dc.conference.place | Banff, AB, Canada | en_US |
| dc.conference.title | Fifth International Workshop on System-on-Chip for Real-Time Applications, 2005 | en_US |
| dc.identifier.tou | http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php | en_US |
| dc.identifier.url | http://ieeexplore.ieee.org/abstract/document/1530964/ | en_US |
| dc.author.affiliation | Lebanese American University | en_US |