Integrated test scheduling, wrapper design, and TAM assignment for hierarchical SOC

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dc.contributor.author Harmanani, Haidar M.
dc.contributor.author Farah, Rana
dc.date.accessioned 2017-03-29T11:47:09Z
dc.date.available 2017-03-29T11:47:09Z
dc.identifier.isbn 978-1-4244-1175-7 en_US
dc.identifier.uri http://hdl.handle.net/10725/5458
dc.description.abstract System-on-chip (SOCs) test minimization has received a lot of attention in the past few years. However, most recent work assumed flat hierarchy. This assumption is unrealistic especially in the case of non-mergeable legacy cores that have been placed and routed. This paper presents an efficient approach for test scheduling hierarchical core-based systems based on simulated annealing. The method minimizes the overall test application time while performing wrapper design and TAM assignment. We present experimental results for various SOC examples that demonstrate the effectiveness of our method. en_US
dc.language.iso en en_US
dc.publisher IEEE en_US
dc.title Integrated test scheduling, wrapper design, and TAM assignment for hierarchical SOC en_US
dc.type Conference Paper / Proceeding en_US
dc.author.school SAS en_US
dc.author.idnumber 199490170 en_US
dc.author.department Computer Science and Mathematics en_US
dc.description.embargo N/A en_US
dc.keywords Job shop scheduling en_US
dc.keywords System testing en_US
dc.keywords Simulated annealing en_US
dc.keywords Circuit testing en_US
dc.keywords Design methodology en_US
dc.keywords Processor scheduling en_US
dc.keywords Computer science en_US
dc.keywords Mathematics en_US
dc.keywords System-on-a-chip en_US
dc.identifier.doi http://dx.doi.org/10.1109/MWSCAS.2007.4488807 en_US
dc.identifier.ctation Harmanani, H. M., & Farah, R. (2007, August). Integrated test scheduling, wrapper design, and TAM assignment for hierarchical SOC. In Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on (pp. 1388-1391). IEEE. en_US
dc.author.email haidar.harmanani@lau.edu.lb en_US
dc.conference.date 5-8 Aug. 2007 en_US
dc.conference.pages 1388-1391 en_US
dc.conference.title 50th Midwest Symposium on Circuits and Systems, 2007 en_US
dc.identifier.tou http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php en_US
dc.identifier.url http://ieeexplore.ieee.org/abstract/document/4488807/ en_US
dc.author.affiliation Lebanese American University en_US

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