Integrated test scheduling, wrapper design, and TAM assignment for hierarchical SOC

Abstract

System-on-chip (SOCs) test minimization has received a lot of attention in the past few years. However, most recent work assumed flat hierarchy. This assumption is unrealistic especially in the case of non-mergeable legacy cores that have been placed and routed. This paper presents an efficient approach for test scheduling hierarchical core-based systems based on simulated annealing. The method minimizes the overall test application time while performing wrapper design and TAM assignment. We present experimental results for various SOC examples that demonstrate the effectiveness of our method.