Test time minimization for system-on-chip with test bus assignment and sizin

LAUR Repository

Show simple item record

dc.contributor.author Harmanani, Haidar M.
dc.contributor.author Sawan, Rachel
dc.date.accessioned 2017-03-29T11:25:58Z
dc.date.available 2017-03-29T11:25:58Z
dc.identifier.isbn 978-1-4244-1163-4 en_US
dc.identifier.uri http://hdl.handle.net/10725/5457
dc.description.abstract Test access is a major problem in testing embedded cores as it directly impacts testing time and hardware cost. Test access mechanism (TAM) is responsible for test data transport and is characterized by its bandwidth capacity. Efficient TAM design is of critical importance in SOC system integration since a test architecture should reduce test cost by minimizing test application time. In this paper, we propose a genetic algorithm to design test access architectures while investigating test bus sizing concurrently with assigning cores to test buses. We present experimental results that demonstrate the effectiveness of the proposed method. en_US
dc.language.iso en en_US
dc.publisher IEEE en_US
dc.title Test time minimization for system-on-chip with test bus assignment and sizin en_US
dc.type Conference Paper / Proceeding en_US
dc.author.school SAS en_US
dc.author.idnumber 199490170 en_US
dc.author.department Computer Science and Mathematics en_US
dc.description.embargo N/A en_US
dc.keywords System testing en_US
dc.keywords System-on-a-chip en_US
dc.keywords Genetic algorithms en_US
dc.keywords Circuit testing en_US
dc.keywords Logic testing en_US
dc.keywords Benchmark testing en_US
dc.keywords Hardware en_US
dc.keywords Costs en_US
dc.keywords Algorithm design and analysis en_US
dc.keywords Niobium en_US
dc.identifier.doi http://dx.doi.org/10.1109/NEWCAS.2007.4488014 en_US
dc.identifier.ctation Harmanani, H. M., & Sawan, R. (2007, August). Test time minimization for system-on-chip with test bus assignment and sizing. In Circuits and Systems, 2007. NEWCAS 2007. IEEE Northeast Workshop on (pp. 1281-1284). IEEE. en_US
dc.author.email haidar.harmanani@lau.edu.lb en_US
dc.conference.date 5-8 Aug. 2007 en_US
dc.conference.pages 1281-1284 en_US
dc.conference.title IEEE Northeast Workshop on Circuits and Systems, 2007 en_US
dc.identifier.tou http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php en_US
dc.identifier.url http://ieeexplore.ieee.org/abstract/document/4488014/ en_US
dc.author.affiliation Lebanese American University en_US

Files in this item

This item appears in the following Collection(s)

Show simple item record

Search LAUR

Advanced Search


My Account