A method for optimizing test bus assignment and sizing for system-on-a-chip

Abstract

Test access mechanism (TAM) is an important element of test access architectures for embedded cores and is responsible for on-chip test patterns transport from the source to the core under test to the sink. Efficient TAM design is of critical importance in SOC system integration since it directly impacts testing time and cost. In this paper, we propose an efficient genetic algorithm to design test access architectures while investigating test bus sizing and assignment of cores to test buses in the system. We present experimental results that demonstrate the effectiveness of our method while outperforming reported techniques.