An Ant Colony Optimization approach for test pattern generation

Harmanani, Haidar M.

An Ant Colony Optimization approach for test pattern generation

Harmanani, Haidar M.

URI: http://hdl.handle.net/10725/5455

URL: http://ieeexplore.ieee.org/abstract/document/4564771/

DOI: http://dx.doi.org/10.1109/CCECE.2008.4564771

Date: 2017-03-29

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Abstract:

Test pattern generation is a challenging problem that has an exponential complexity that is aggravated with the continuos increase in circuits size. This paper deals with automatic test pattern generation (ATPG) for combinational circuits, and proposes a new approach based on Ant Colony Optimization (ACO). The paper studies the opportunities offered by ACO in comparison with other simulated-based ATPGs. The method is implemented and is shown to efficiently generate a set of test vectors that achieve a high fault coverage in a short time. Several benchmark circuits are attempted, and favorable results comparisons are reported

Citation:

Farah, R., & Harmanani, H. M. (2008, May). An Ant Colony Optimization approach for test pattern generation. In Electrical and Computer Engineering, 2008. CCECE 2008. Canadian Conference on (pp. 001397-001402). IEEE.