A method for efficient mapping and reliable routing for NoC architectures with minimum bandwidth and area

Abstract

Network-on-Chip (NoC) is an on-chip communication methodology that has been proposed as an alternative to bus-based communication in order to cope with the increased complexity in embedded designs. This paper presents a method for assigning tasks to nodes in a 2-D mesh, and for determining the nodes positions on the mesh using simulated annealing. The method proposes a new efficient routing algorithm that minimizes blocking while increasing bandwidth throughput. The method is implemented and various benchmarks are attempted.