Integrating wrapper design, TAM assignment, and test scheduling for SOC test optimization

Harmanani, Haidar M.; Farah, Rana

Integrating wrapper design, TAM assignment, and test scheduling for SOC test optimization

Harmanani, Haidar M.; Farah, Rana

URI: http://hdl.handle.net/10725/5453

URL: http://ieeexplore.ieee.org/abstract/document/4606343/

DOI: http://dx.doi.org/10.1109/NEWCAS.2008.4606343

Date: 2017-03-29

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Abstract:

Test time minimization for core-based designs is tightly integrated with wrapper design and TAM capacity. This paper presents a method to determine minimum SOC test schedules with wrapper design and TAM optimization based on simulated annealing. The method can handle SOC test scheduling with and without power constraints in addition to precedence constraints that preserve desirable orderings among tests. We present experimental results using the ITC 2002 benchmarks.

Citation:

Harmanani, H. M., & Farah, R. (2008, June). Integrating wrapper design, TAM assignment, and test scheduling for SOC test optimization. In Circuits and Systems and TAISA Conference, 2008. NEWCAS-TAISA 2008. 2008 Joint 6th International IEEE Northeast Workshop on (pp. 149-152). IEEE.