Estimating test cost during data path and controller synthesis with low power overhead

Harmanani, Haidar M.; Kodeih, Maya

Estimating test cost during data path and controller synthesis with low power overhead

Harmanani, Haidar M.; Kodeih, Maya

URI: http://hdl.handle.net/10725/5452

URL: http://ieeexplore.ieee.org/abstract/document/5575139/

DOI: http://dx.doi.org/10.1109/CCECE.2010.5575139

Date: 2017-03-29

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Abstract:

This paper presents a method for concurrent BIST cost estimation during testable data path allocation. The method integrates testability in the design process and generates a distributed test controller that aims to minimize area and power. The system has been implemented and favorable results are reported.

Citation:

Harmanani, H. M., & Kodeih, M. (2010, May). Estimating test cost during data path and controller synthesis with low power overhead. In Electrical and Computer Engineering (CCECE), 2010 23rd Canadian Conference on (pp. 1-5). IEEE.