A method for efficient NoC test scheduling using deterministic routing

Harmanani, Haidar; Farah, Rana

dc.contributor.author	Harmanani, Haidar
dc.contributor.author	Farah, Rana
dc.date.accessioned	2017-03-29T08:16:13Z
dc.date.available	2017-03-29T08:16:13Z
dc.date.issued	2017-03-29
dc.identifier.isbn	978-1-4244-6683-2	en_US
dc.identifier.uri	http://hdl.handle.net/10725/5451
dc.description.abstract	Network-on-Chip (NoC) is an on-chip communication methodology that has been proposed as an alternative to bus-based communication in order to cope with the increased complexity in embedded designs. This paper presents a method for NoCs test scheduling using simulated annealing. The method uses a deterministic routing algorithm that minimizes test time while avoiding blocking. The method is implemented and various benchmarks are attempted.	en_US
dc.language.iso	en	en_US
dc.publisher	IEEE	en_US
dc.title	A method for efficient NoC test scheduling using deterministic routing	en_US
dc.type	Conference Paper / Proceeding	en_US
dc.author.school	SAS	en_US
dc.author.idnumber	199490170	en_US
dc.author.department	Computer Science and Mathematics	en_US
dc.description.embargo	N/A	en_US
dc.keywords	Switches	en_US
dc.keywords	Annealing	en_US
dc.keywords	Niobium	en_US
dc.identifier.doi	http://dx.doi.org/10.1109/SOCC.2010.5784696	en_US
dc.identifier.ctation	Farah, R., & Harmanani, H. (2010, September). A method for efficient NoC test scheduling using deterministic routing. In SOC Conference (SOCC), 2010 IEEE International (pp. 363-366). IEEE.	en_US
dc.author.email	haidar.harmanani@lau.edu.lb	en_US
dc.conference.date	27-29 Sept. 2010	en_US
dc.conference.pages	363-366	en_US
dc.conference.place	Las Vegas, USA	en_US
dc.conference.title	2010 IEEE International SOC Conference	en_US
dc.identifier.tou	http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php	en_US
dc.identifier.url	http://ieeexplore.ieee.org/abstract/document/5784696/	en_US
dc.author.affiliation	Lebanese American University	en_US