A method for efficient NoC test scheduling using deterministic routing

Harmanani, Haidar; Farah, Rana

A method for efficient NoC test scheduling using deterministic routing

Harmanani, Haidar; Farah, Rana

URI: http://hdl.handle.net/10725/5451

URL: http://ieeexplore.ieee.org/abstract/document/5784696/

DOI: http://dx.doi.org/10.1109/SOCC.2010.5784696

Date: 2017-03-29

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Abstract:

Network-on-Chip (NoC) is an on-chip communication methodology that has been proposed as an alternative to bus-based communication in order to cope with the increased complexity in embedded designs. This paper presents a method for NoCs test scheduling using simulated annealing. The method uses a deterministic routing algorithm that minimizes test time while avoiding blocking. The method is implemented and various benchmarks are attempted.

Citation:

Farah, R., & Harmanani, H. (2010, September). A method for efficient NoC test scheduling using deterministic routing. In SOC Conference (SOCC), 2010 IEEE International (pp. 363-366). IEEE.