dc.contributor.author |
Harmanani, Haidar M. |
|
dc.contributor.author |
Ferzli, Rony |
|
dc.contributor.author |
Anabtawi, Nijad |
|
dc.date.accessioned |
2017-03-28T09:31:39Z |
|
dc.date.available |
2017-03-28T09:31:39Z |
|
dc.date.issued |
2017-03-28 |
|
dc.identifier.isbn |
978-1-4799-5341-7 |
en_US |
dc.identifier.uri |
http://hdl.handle.net/10725/5441 |
|
dc.description.abstract |
This paper presents a switching DC-DC Buck converter with enhanced light-load efficiency for use in noise-sensitive applications. Low noise, spur free operation is achieved by using a sigma-delta-modulator (ΣΔ) based controller, while light load efficiency is realized through the introduction of fine step frequency scaling (FSFS) which continuously adjusts the switching frequency of the converter with load conditions. Regulation efficiency is further improved by adoption of mode hopping (continuous conduction mode (CCM)/ discontinuous conduction mode (DCM)) and utilization of a fully digital implementation. Furthermore, the presented converter maintains low output voltage ripple across its entire load range by reconfiguring the ΣΔ modulator's quantization step and introducing dither to the loop filter. The proposed modulator was implemented in 14nm bulk CMOS process and validated with post layout simulations. It attains a peak efficiency of 95% at heavy load conditions and 79% at light loads with a maximum voltage ripple of 15mV at light loads. |
en_US |
dc.language.iso |
en |
en_US |
dc.publisher |
IEEE |
en_US |
dc.title |
An enhanced light-load efficiency step down regulator with fine step frequency scaling |
en_US |
dc.type |
Conference Paper / Proceeding |
en_US |
dc.author.school |
SAS |
en_US |
dc.author.idnumber |
199490170 |
en_US |
dc.author.department |
Computer Science and Mathematics |
en_US |
dc.description.embargo |
N/A |
en_US |
dc.identifier.doi |
http://dx.doi.org/10.1109/ISCAS.2016.7539149 |
en_US |
dc.identifier.ctation |
Anabtawi, N., Ferzli, R., & Harmanani, H. M. (2016, May). An enhanced light-load efficiency step down regulator with fine step frequency scaling. In Circuits and Systems (ISCAS), 2016 IEEE International Symposium on (pp. 2695-2698). IEEE. |
en_US |
dc.author.email |
haidar.harmanani@lau.edu.lb |
en_US |
dc.conference.date |
22-25 May 2016 |
en_US |
dc.conference.pages |
2695-2698 |
en_US |
dc.conference.place |
Montréal, QC, Canada |
en_US |
dc.conference.title |
2016 IEEE International Symposium on Circuits and Systems |
en_US |
dc.identifier.tou |
http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php |
en_US |
dc.identifier.url |
http://ieeexplore.ieee.org/abstract/document/7539149/ |
en_US |
dc.author.affiliation |
Lebanese American University |
en_US |