Multigrid solvers in reconfigurable hardware

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dc.contributor.author Haraty, Ramzi A.
dc.contributor.author Kasbah, Safaa J.
dc.contributor.author Damaj, Issam W.
dc.date.accessioned 2017-01-31T09:38:41Z
dc.date.available 2017-01-31T09:38:41Z
dc.date.copyright 2008 en_US
dc.date.issued 2017-01-31
dc.identifier.issn 0377-0427 en_US
dc.identifier.uri http://hdl.handle.net/10725/5115
dc.description.abstract The problem of finding the solution of partial differential equations (PDEs) plays a central role in modeling real world problems. Over the past years, Multigrid solvers have showed their robustness over other techniques, due to its high convergence rate which is independent of the problem size. For this reason, many attempts for exploiting the inherent parallelism of Multigrid have been made to achieve the desired efficiency and scalability of the method. Yet, most efforts fail in this respect due to many factors (time, resources) governed by software implementations. In this paper, we present a hardware implementation of the V-cycle Multigrid method for finding the solution of a 2D-Poisson equation. We use Handel-C to implement our hardware design, which we map onto available field programmable gate arrays (FPGAs). We analyze the implementation performance using the FPGA vendor's tools. We demonstrate the robustness of Multigrid over other similar iterative solvers, such as Jacobi and successive over relaxation (SOR ), in both hardware and software. We compare our findings with a C++ version of each algorithm. The obtained results show better performance when compared to existing software versions. en_US
dc.language.iso en en_US
dc.title Multigrid solvers in reconfigurable hardware en_US
dc.type Article en_US
dc.description.version Published en_US
dc.author.school SAS en_US
dc.author.idnumber 199729410 en_US
dc.author.department Computer Science and Mathematics en_US
dc.description.embargo N/A en_US
dc.relation.journal Journal of Computational and Applied Mathematics en_US
dc.journal.volume 213 en_US
dc.journal.issue 1 en_US
dc.article.pages 79-94 en_US
dc.keywords Iterative methods en_US
dc.keywords Parallelization en_US
dc.keywords FPGA en_US
dc.keywords Reconfigurable computing en_US
dc.identifier.doi http://dx.doi.org/10.1016/j.cam.2006.12.031 en_US
dc.identifier.ctation Kasbah, S. J., Damaj, I. W., & Haraty, R. A. (2008). Multigrid solvers in reconfigurable hardware. Journal of Computational and Applied Mathematics, 213(1), 79-94. en_US
dc.author.email rharaty@lau.edu.lb en_US
dc.identifier.tou http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php en_US
dc.identifier.url http://www.sciencedirect.com/science/article/pii/S0377042707000076?np=y&npKey=f5e3b7a1bc9583215101df125b4bb63df852cf5061b01229a0f8639840bb9e29 en_US
dc.orcid.id https://orcid.org/0000-0002-6978-3627
dc.author.affiliation Lebanese American University en_US

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