Optimizing Functional Unit Binding During HighLevel Synthesis

Abstract

One of the three central synthesis tasks in a typical high-level synthesis system is binding which assigns operations to functional units, values to storage units, and interconnects these components with wires and buses to form a complete data path. The data path constitutes a considerable area of an application specific integrated circuit (ASIC) or field-programmable gate array (FPGA). This article proposes a solution that incorporates a simulated annealing approach after binding operations to functional units in the goal of reducing overall area. When standard scheduling techniques are used, this solution assigns operations to the same hardware resource when those operations’ inputs or outputs are bound to the same storage units. The optimization procedure swaps possible nodes to decrease the number of needed multiplexers in the final design. In typical benchmarks, the savings obtained in terms of multiplexer area reach 33.6% with an average of 17.1%; moreover, the overall logic area savings reach 18.2% with an average of 6.6%