Optimizing Functional Unit Binding During HighLevel Synthesis

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dc.contributor.author Ouaiss, Iyad
dc.contributor.author Bassil, Layale
dc.date.accessioned 2016-11-24T13:00:36Z
dc.date.available 2016-11-24T13:00:36Z
dc.date.copyright 2012 en_US
dc.date.issued 2016-11-24
dc.identifier.issn 1206-212X en_US
dc.identifier.uri http://hdl.handle.net/10725/4854
dc.description.abstract One of the three central synthesis tasks in a typical high-level synthesis system is binding which assigns operations to functional units, values to storage units, and interconnects these components with wires and buses to form a complete data path. The data path constitutes a considerable area of an application specific integrated circuit (ASIC) or field-programmable gate array (FPGA). This article proposes a solution that incorporates a simulated annealing approach after binding operations to functional units in the goal of reducing overall area. When standard scheduling techniques are used, this solution assigns operations to the same hardware resource when those operations’ inputs or outputs are bound to the same storage units. The optimization procedure swaps possible nodes to decrease the number of needed multiplexers in the final design. In typical benchmarks, the savings obtained in terms of multiplexer area reach 33.6% with an average of 17.1%; moreover, the overall logic area savings reach 18.2% with an average of 6.6% en_US
dc.language.iso en en_US
dc.title Optimizing Functional Unit Binding During HighLevel Synthesis en_US
dc.type Article en_US
dc.description.version Published en_US
dc.author.school SOE en_US
dc.author.idnumber 200105659 en_US
dc.author.department Electrical And Computer Engineering en_US
dc.description.embargo N/A en_US
dc.relation.journal International Journal of Computers and Applications en_US
dc.journal.volume 34 en_US
dc.journal.issue 1 en_US
dc.article.pages 58-65 en_US
dc.keywords High-level synthesis en_US
dc.keywords Resource binding en_US
dc.keywords Scheduling en_US
dc.keywords Simulated annealing en_US
dc.identifier.doi http://dx.doi.org/10.2316/Journal.202.2012.1.202-3223 en_US
dc.identifier.ctation Bassil, L., & Ouaiss, I. (2012). Optimizing Functional Unit Binding During High-Level Synthesis. International Journal of Computers and Applications, 34(1), 58-65. en_US
dc.author.email iiyad.ouaiss@lau.edu.lb en_US
dc.identifier.tou http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php en_US
dc.identifier.url http://www.tandfonline.com/doi/abs/10.2316/Journal.202.2012.1.202-3223 en_US
dc.author.affiliation Lebanese American University en_US

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