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Enhanced Technology Mapping for FPGAs with Exploration of Cell Configurations

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dc.contributor.author Ouaiss, Iyad
dc.contributor.author Zgheib, Grace
dc.date.accessioned 2016-11-24T12:55:04Z
dc.date.available 2016-11-24T12:55:04Z
dc.date.copyright 2015 en_US
dc.identifier.issn 0218-1266 en_US
dc.identifier.uri http://hdl.handle.net/10725/4853
dc.description.abstract In the state-of-the-art field-programmable gate arrays (FPGAs), logic circuits are synthesized and mapped on clusters of look-up tables. However, arithmetic operations benefit from an existing dedicated adder along with a carry chain used to ensure a fast carry propagation. This carry chain is a dedicated wire available in the architecture of the FPGA and is as such independent of the external programmable routing resources. In this paper, we propose a variable-structure Boolean matching technology mapper with embedded decomposition techniques to map nonarithmetic logic functions on carry chains. Previously synthesized and mapped logic functions are adapted so that their outputs are routed using the dedicated carry chains instead of the external programmable interconnects. The experimental results show a reduction in the used routing resources as well as the circuit area when using this Boolean matching-based mapper on the Altera Stratix-III FPGA. en_US
dc.language.iso en en_US
dc.title Enhanced Technology Mapping for FPGAs with Exploration of Cell Configurations en_US
dc.type Article en_US
dc.description.version Published en_US
dc.author.school SOE en_US
dc.author.idnumber 200105659 en_US
dc.author.department Electrical And Computer Engineering en_US
dc.description.embargo N/A en_US
dc.relation.journal Journal of Circuits, Systems and Computers en_US
dc.journal.volume 24 en_US
dc.journal.issue 3 en_US
dc.article.pages 1-19 en_US
dc.keywords Field programmable gate array en_US
dc.keywords Technology mapping en_US
dc.keywords Boolean matching en_US
dc.keywords Decomposition en_US
dc.keywords Carry chain en_US
dc.keywords Cell configuration en_US
dc.identifier.doi http://dx.doi.org/10.1142/S0218126615500395 en_US
dc.identifier.ctation Zgheib, G., & Ouaiss, I. (2015). Enhanced technology mapping for FPGAs with exploration of cell configurations. Journal of Circuits, Systems and Computers, 24(03), 1550039. en_US
dc.author.email iiyad.ouaiss@lau.edu.lb en_US
dc.identifier.tou http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php en_US
dc.identifier.url http://www.worldscientific.com/doi/abs/10.1142/S0218126615500395 en_US
dc.author.affiliation Lebanese American University en_US


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