An interactive approach for trading test time, area, and fault coverage in testable synthesis. (c2006)

Abstract

Over the past decade circuits' complexity has increased while the transistor count on a single chip increased tremendously. Research on computer-aided design (CAD) tools also progressed as circuit complexity increased. This increase in circuits' complexity led to the appearance of High-Level synthesis. High-Level synthesis can capture system specification at a higher level of abstraction, which will reduce the circuit design complexity. In this Thesis, we develop a High-level synthesis prototype that is flexible and that allows designers to interact with the system through a graphical user interface. This tool can be easily extended and new features can be implemented and plugged in without difficulties. The goal for a High-Level synthesis tool is the generation of a data path from the circuit's behavioral description. This thesis presents a method for interactive test synthesis for RTL designs. The method provides a mechanism to redesign RTL data path into testable ones while performing the allocation of functional units, registers, and interconnects. Our tool implements the main functions in a high-level synthesis and it proposes techniques for the allocation task that uses an iterative improvement optimization method that minimizes the area and power consumption. The system has been implemented using Java and favorable results are reported.