Abstract:
The increasing density in VLSI chips complicates the design as well as it complicates the testability problem. This thesis proposes a new approach to redesign for testability at the Register Transfer Level (RTL). Given an RTL description of a data path, the purpose of the redesign process is to improve its testability with a minimal cost by: 1) inserting additional registers, if necessary; 2) Converting already existing registers into test registers so that they can be configured as TPGRs, MISRs, or BILBOs during test mode. In order to reduce test penalty, and insure the data path structural testability, it is necessary to automate the BIST Insertion process. BIST registers are chosen so that to minimize test and time overhead, by using Randomness and Transparency metrics of the combinational logic.
