Concurrent BIST Synthesis and Test Scheduling Using Genetic Algorithms

Abstract

This paper presents an efficient method for concurrent built-in self-test synthesis and test scheduling in high-level synthesis. The method maximizes concurrent testing of modules while performing the allocation of functional units, test registers, and interconnects. The method is based on a genetic algorithm that efficiently explores the testable design space and finds a sub-optimal test registers assignment for each k-test session. The method was implemented using C+ + on a Linux workstation. Several benchmark examples have been implemented and favorable design comparisons are reported.