Power-constrained system-on-a-chip test scheduling using a genetic algorithm

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dc.contributor.author Harmanani, Haidar M.
dc.contributor.author Salamy, Hassan A.
dc.date.accessioned 2016-04-11T12:47:00Z
dc.date.available 2016-04-11T12:47:00Z
dc.date.copyright 2006
dc.date.issued 2016-04-11
dc.identifier.issn 0218-1266 en_US
dc.identifier.uri http://hdl.handle.net/10725/3529
dc.description.abstract This paper presents an efficient approach for the test scheduling problem of core-based systems based on a genetic algorithm. The method minimizes the overall test application time of a system-on-a-chip through efficient and compact test schedules. The problem is solved using a "sessionless" scheme that minimizes the number of idle test slots. The method can handle SOC test scheduling with and without power constraints. We present experimental results for various SOC examples that demonstrate the effectiveness of our method. The method achieved optimal test schedules in all attempted cases in a short CPU time. en_US
dc.language.iso en en_US
dc.title Power-constrained system-on-a-chip test scheduling using a genetic algorithm en_US
dc.type Article en_US
dc.description.version Published en_US
dc.author.school SAS en_US
dc.author.idnumber 199490170 en_US
dc.author.woa N/A en_US
dc.author.department Computer Science and Mathematics en_US
dc.description.embargo N/A en_US
dc.relation.journal Journal of Circuits, Systems and Computers en_US
dc.journal.volume 15 en_US
dc.journal.issue 3 en_US
dc.article.pages 331-349 en_US
dc.keywords Core-based systems en_US
dc.keywords Embedded core testing en_US
dc.keywords Genetic algorithms en_US
dc.identifier.doi http://dx.doi.org/10.1142/S0218126606003106
dc.identifier.ctation Harmanani, H. M., & Salamy, H. A. (2006). Power-constrained system-on-a-chip test scheduling using a genetic algorithm. Journal of Circuits, Systems, and Computers, 15(03), 331-349. en_US
dc.author.email haidar.harmanani@lau.edu.lb
dc.identifier.url http://www.worldscientific.com/doi/abs/10.1142/S0218126606003106

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