Test bus assignment, sizing, and partitioning for system-on-chip

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dc.contributor.author Harmanani, Haidar M.
dc.contributor.author Sawan, Rachel
dc.date.accessioned 2016-04-11T12:37:51Z
dc.date.available 2016-04-11T12:37:51Z
dc.date.copyright 2007
dc.date.issued 2017-08-10
dc.identifier.issn 0840-8688 en_US
dc.identifier.uri http://hdl.handle.net/10725/3528
dc.description.abstract The test access mechanism (TAM) is an important element of test architectures for embedded cores and is responsible for on-chip test pattern transport from the source to the core under test to the sink. Efficient TAM design is of critical importance in system-on-chip integration since it directly impacts testing time and hardware cost. In this paper, an efficient genetic algorithm for designing test access architectures while investigating test bus sizing and concurrently assigning cores to test buses is proposed. Experimental results are presented to demonstrate that the proposed TAM optimization methodology provides efficient test bus designs with minimum testing time while outperforming reported techniques. en_US
dc.language.iso en en_US
dc.title Test bus assignment, sizing, and partitioning for system-on-chip en_US
dc.type Article en_US
dc.description.version Published en_US
dc.author.school SAS en_US
dc.author.idnumber 199490170 en_US
dc.author.woa N/A en_US
dc.author.department Computer Science and Mathematics en_US
dc.description.embargo N/A en_US
dc.relation.journal Canadian Journal of Electrical and Computer Engineering en_US
dc.journal.volume 32 en_US
dc.journal.issue 3 en_US
dc.article.pages 165-175 en_US
dc.identifier.doi http://dx.doi.org/10.1109/CJECE.2007.4413128 en_US
dc.identifier.ctation Harmanani, H. M., & Sawan, R. (2007). Test bus assignment, sizing, and partitioning for system-on-chip. Electrical and Computer Engineering, Canadian Journal of, 32(3), 165-175. en_US
dc.author.email haidar.harmanani@lau.edu.lb
dc.identifier.url http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4413128

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