KT2C. (c2014)

Abstract

We introduce the K-way Thermal Chip Clustering (KT2C) algorithm; a VLSI chip partitioning algorithm that is used to reduce the chip’s temperature and prevent the formation of hotspots. The clustering algorithm is integrated in the design flow between the stages of binding and floor-planning. KT2C uses power and area information from a component library to identify the components that will most probably result in hotspots. These components are labeled as thermal centers which then form independent clusters. The rest of the components are distributed among these clusters with the goal of reducing the center's temperature. The algorithm then iterates attempting to produce a uniform temperature distribution among clusters while reducing wire-length. Upon convergence, the components undergo two stages of floor-planning. At the intra-cluster floor-planning stage, the positions of the components inside each cluster are determined, whereas in the inter-cluster floor-planning stage the position of each cluster block on the chip is determined. The temperature profile of the resulting chip is calculated using the thermal simulator “Hotspot” and is compared to the temperature profile of a design achieved using a regular design flow. The results show significant reduction in both average and peak temperatures at the cost of a small increase in area. Furthermore, when optimizing for wire-length, KT2C produced a remarkable reduction in total wire-length which surpassed the reduction achieved by the non-clustering solution. Finally, a parallel design of the KT2C design flow was proposed and the conducted timing analysis showed that large speedups could be achieved if parallelism was implemented.