A Novel Register Binding Approach to Reduce Spurious Switching Activity in High-Level Synthesis

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dc.contributor.author Ouaiss, Iyad
dc.contributor.author Elaaraj, Elie
dc.date.accessioned 2016-02-24T13:19:14Z
dc.date.available 2016-02-24T13:19:14Z
dc.date.copyright 2011
dc.date.issued 2016-02-24
dc.identifier.issn 0218-1266 en_US
dc.identifier.uri http://hdl.handle.net/10725/3170
dc.description.abstract Optimizing area and timing have long been considered to be the main design challenges in high-level synthesis. A lot of research has been conducted in this area and many techniques to improve performance have been suggested. However, as design applications become more power-sensitive, and with the emergence of portable devices that operate under stringent power constraints, power consumption surfaced as a major issue to be considered in the design and optimization processes. This work studies the effects of binding and scheduling on power consumption in high-level synthesis by analyzing unnecessary switching. The major contribution of this work is to reduce the unnecessary switching at the inputs of a circuit's functional units, referred to as spurious switching activities. For this purpose, all spurious and nonspurious switching inputs in a circuit were identified, and many techniques were studied to find the optimal register bindings without inducing any increase in the number of storage elements. Power reduction was attained through altering register bindings using a cool-down simulated annealing approach. To test these techniques, a high-level synthesis environment, "Eridanus", was developed and several benchmarks, consisting of various complexities, have been tested. Using the approach suggested in this work, spurious switching activity was reduced by 40% on average. en_US
dc.language.iso en en_US
dc.title A Novel Register Binding Approach to Reduce Spurious Switching Activity in High-Level Synthesis en_US
dc.type Article en_US
dc.description.version Published en_US
dc.author.school SOE en_US
dc.author.idnumber 200105659 en_US
dc.author.woa N/A en_US
dc.author.department Electrical Engineering en_US
dc.description.embargo N/A en_US
dc.relation.journal Journal of Circuits, Systems and Computers en_US
dc.journal.volume 20 en_US
dc.journal.issue 5 en_US
dc.article.pages 943-973 en_US
dc.keywords High-level synthesis en_US
dc.keywords Resource management en_US
dc.keywords Scheduling en_US
dc.keywords Dynamic power reduction en_US
dc.keywords Spurious switching activity en_US
dc.identifier.doi http://dx.doi.org/10.1142/S0218126611007700 en_US
dc.identifier.ctation Elaaraj, E., & Ouaiss, I. (2011). A NOVEL REGISTER-BINDING APPROACH TO REDUCE SPURIOUS SWITCHING ACTIVITY IN HIGH-LEVEL SYNTHESIS. Journal of Circuits, Systems, and Computers, 20(05), 943-973. en_US
dc.author.email iyad.ouaiss@lau.edu.lb
dc.identifier.url http://www.worldscientific.com/doi/abs/10.1142/S0218126611007700

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