Priority-Driven Area Optimization in High-Level Synthesis

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dc.contributor.author Abi Saad, Maria
dc.contributor.author Ouaiss, Iyad
dc.date.accessioned 2016-02-24T13:11:47Z
dc.date.available 2016-02-24T13:11:47Z
dc.date.copyright 2011
dc.date.issued 2016-02-24
dc.identifier.issn 0218-1266 en_US
dc.identifier.uri http://hdl.handle.net/10725/3169
dc.description.abstract One of the major enhancements that can be made to the high-level synthesis (HLS) process is reducing the overall area of a design in order to either decrease the manufacturing costs or to introduce more functionality to the circuit. Optimizing the area of the datapath is considered a primary field of research in HLS. This work proposes an approach to reduce the area in field programmable gate array (FPGA) by simultaneously tackling the three central tasks of HLS. Scheduling, allocation, and binding are performed and the optimal solution based on area reduction is obtained by using simulated annealing with a priority function. The aim of the priority function is to guide the simulated annealing process into finding the best solution while at the same time incurring the least possible execution time. In order to achieve better results than the initial solution, rescheduling, swapping operations between functional units, swapping variables between registers, and swapping inputs to functional units are considered in the annealing process. A cost function is devised to evaluate a potential move's success or failure. The simulation environment "Eridanus" has been developed in order to support implementation and testing. Several benchmarks were tested and the numerical results consisting of the execution time along with the best solution were recorded to illustrate the performance of the proposed technique. Area reduction was obtained compared to the conventional HLS flow; furthermore, an average substantial reduction in design space exploration time was obtained compared to non-priority based area optimization techniques. en_US
dc.language.iso ar en_US
dc.title Priority-Driven Area Optimization in High-Level Synthesis en_US
dc.type Article en_US
dc.description.version Published en_US
dc.author.school SOE en_US
dc.author.idnumber 200105659 en_US
dc.author.woa N/A en_US
dc.author.department Electrical Engineering en_US
dc.description.embargo N/A en_US
dc.relation.journal Journal of Circuits, Systems and Computers en_US
dc.journal.volume 20 en_US
dc.journal.issue 6 en_US
dc.keywords Simulated annealing en_US
dc.keywords High-level synthesis en_US
dc.keywords Scheduling en_US
dc.keywords Resource management en_US
dc.identifier.doi http://dx.doi.org/10.1142/S0218126611007803 en_US
dc.identifier.ctation Saad, M. A., & Ouaiss, I. (2011). PRIORITY-DRIVEN AREA OPTIMIZATION IN HIGH-LEVEL SYNTHESIS. Journal of Circuits, Systems, and Computers, 20(06), 1131-1163. en_US
dc.author.email iyad.ouaiss@lau.edu.lb
dc.identifier.url http://www.worldscientific.com/doi/abs/10.1142/S0218126611007803

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