Priority-Driven Area Optimization in High-Level Synthesis

Abstract

One of the major enhancements that can be made to the high-level synthesis (HLS) process is reducing the overall area of a design in order to either decrease the manufacturing costs or to introduce more functionality to the circuit. Optimizing the area of the datapath is considered a primary field of research in HLS. This work proposes an approach to reduce the area in field programmable gate array (FPGA) by simultaneously tackling the three central tasks of HLS. Scheduling, allocation, and binding are performed and the optimal solution based on area reduction is obtained by using simulated annealing with a priority function. The aim of the priority function is to guide the simulated annealing process into finding the best solution while at the same time incurring the least possible execution time. In order to achieve better results than the initial solution, rescheduling, swapping operations between functional units, swapping variables between registers, and swapping inputs to functional units are considered in the annealing process. A cost function is devised to evaluate a potential move's success or failure. The simulation environment "Eridanus" has been developed in order to support implementation and testing. Several benchmarks were tested and the numerical results consisting of the execution time along with the best solution were recorded to illustrate the performance of the proposed technique. Area reduction was obtained compared to the conventional HLS flow; furthermore, an average substantial reduction in design space exploration time was obtained compared to non-priority based area optimization techniques.