Parallel multi-voltage power minimization in VLSI circuits. (c2013)

Abstract

Power consumption minimization is nowadays considered a main challenge to VLSI designers, especially with the growth of the mobile computing industry. Previous studies have tried minimizing power consumption at the expense of the overall circuit delay, and have mostly focused at optimizing power at the lower levels of abstraction – during placement and routing. This work presents novel techniques to minimize power consumption during behavioral synthesis and to reduce execution runtime through parallel processing. Design space exploration at higher levels of abstraction yields greater optimization in power, area, and delay; thus, the first contribution intelligently reduces voltages of non-critical paths in order to decrease total power consumption at the behavioral level. Voltage reductions are performed while minimizing the number of voltage conversions introduced in the circuit and maintaining the critical path delay. The second contribution concentrates on exploiting parallelism by distributing independent synthesis tasks to different processing units in the goal of reducing solution exploration time. A synthesis software suite was implemented to test the proposed approaches. Power consumption was reduced considerably with a negligible overhead of voltage conversion modules. Furthermore, design space exploration time declined significantly due to the use of parallel programming.