Efficient techniques for testing networks on chips. (c2010)

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dc.contributor.author Abou Eid, Nancy
dc.date.accessioned 2010-12-20T09:06:18Z
dc.date.available 2010-12-20T09:06:18Z
dc.date.copyright 2010 en_US
dc.date.issued 2010-12-20
dc.date.submitted 5/20/2010
dc.identifier.uri http://hdl.handle.net/10725/164
dc.description Includes bibliographical references (leaves 67-69). en_US
dc.description.abstract Network-on-Chip (NoC) is a new technology that embeds heterogeneous intercon- nected cores. NoC's design is based on a selected network topology, a switching tech- nique and a routing strategy in order to allow on chip communication. Its advantages over System-on-Chip (SoC) are that NoC provides modularity, higher performance, better structure, and compatibility with core designs and reuse. Trades-o exist be- tween them. In this thesis, we tackle the NoC core testing time problem. We use a grid topology, a variable Test Access Mechanism (TAM), a computed optimal it size based on the bandwidth and bu er size, the standard test wrapper, and XY routing strategy. Our goal is to test all cores, under the above constraints, while minimizing overall NoC test time. For this purpose, we have partitioned the cores into sets using two partitioning techniques. The rst is based on grouping together all cores that have similar or close core testing time, and the second is partitioned based on the lower bound computed for each benchmark. In order to evaluate our work, we present experimental results that are compared to each other. en_US
dc.language.iso en en_US
dc.subject Networks on a chip en_US
dc.title Efficient techniques for testing networks on chips. (c2010) en_US
dc.type Thesis en_US
dc.term.submitted Spring en_US
dc.author.degree MS in Computer Science en_US
dc.author.school Arts and Sciences en_US
dc.author.idnumber 200801293 en_US
dc.author.commembers Dr. Danielle Azar
dc.author.commembers Dr. Chadi Nour
dc.author.woa OA en_US
dc.description.physdesc 1 bound copy: xi, 67 leaves; col. ill.; 30 cm. available at RNL. en_US
dc.author.division Computer Science en_US
dc.author.advisor Dr. Haidar Harmanani
dc.identifier.doi https://doi.org/10.26756/th.2010.19 en_US
dc.publisher.institution Lebanese American University en_US
dc.author.affiliation Lebanese American University en_US

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