Efficient techniques for testing networks on chips. (c2010)

Abstract

Network-on-Chip (NoC) is a new technology that embeds heterogeneous intercon- nected cores. NoC's design is based on a selected network topology, a switching tech- nique and a routing strategy in order to allow on chip communication. Its advantages over System-on-Chip (SoC) are that NoC provides modularity, higher performance, better structure, and compatibility with core designs and reuse. Trades-o exist be- tween them. In this thesis, we tackle the NoC core testing time problem. We use a grid topology, a variable Test Access Mechanism (TAM), a computed optimal it size based on the bandwidth and bu er size, the standard test wrapper, and XY routing strategy. Our goal is to test all cores, under the above constraints, while minimizing overall NoC test time. For this purpose, we have partitioned the cores into sets using two partitioning techniques. The rst is based on grouping together all cores that have similar or close core testing time, and the second is partitioned based on the lower bound computed for each benchmark. In order to evaluate our work, we present experimental results that are compared to each other.