Abstract:
High-level synthesis (HLS) scheduling, an NP-hard problem, is a process that auto-mates VLSI design and is a very important step in silicon compilation. HLS takes as input a behavioral description of a system with a set of constraints and outputs an RTL description of a digital system. The two main steps in HLS are: operations scheduling and data-path allocation. In this work, we present a resource constrained scheduling approach that minimizes latency and subject to resource constraints using a deep Q learning algorithm.
The actions and rewards for the proposed algorithm are selected carefully to guide the agent to its objective. We used a deep neural network to train the agent and in order to learn the the Q-values. The results of this work are compared to other state-of-the-art algorithms and are proven to be very effective and promising.
