Abstract:
The increase in density that the advent of Very Large Scale Integration (VLSI) has made the move to higher levels of design abstraction imperative. High Level Synthesis (HLS) emerged as a viable approach that has been gaining strides in the EDA industry. This work exploits the tight relation that exists between the allocation process and chip layout in an integrated system level design environment. The approach proposes a layout-driven data path allocation method, and explores design tradeoffs
among operators binding, registers assignments, and flooplanning shape functions. The approach uses Deep Reinforcement Learning and proposes new methods and tools for the automatic synthesis of data path at the register-transfer level (RTL). A major effort in this research involves the development of a prototype high-level synthesis system that bridges the gap between high level synthesis and layout information. The goal is to build a model capable of learning optimization steps. The approach has
been implemented and several designs were implemented.
