A novel approach to reduce spurious switching activity in high-level synthesis. (c2009)

Abstract

Optimizing area and timing have long been considered to be the main design challenges in high-level synthesis. A lot of research has been conducted in this area and many techniques to improve performance have been suggested. However, as design applications become more power sensitive, and with the emergence of portable devices that operate under stringent power constraints, power consumption surfaced as a major issue to consider in the design and optimization processes. This work studies the effects of binding and scheduling on power consumption in high-level synthesis by analyzing unnecessary switching. The major contribution of this work is to reduce the spurious switching activities in a circuit. For this purpose, all spurious and non-spurious switching inputs in a circuit were identified and many techniques were studied to find the optimal register bindings without inducing any increase in the number of storage elements. Power reduction was attained through altering register bindings using a cool-down simulated annealing approach. In order to test these techniques, a high-level synthesis environment, "Eridanus", was developed and several benchmarks consisting of various complexities have been tested. Using the approach suggested in this work, spurious switching activity was reduced by 40% on average.