We present an automated temporal partitioning tool for developing dynamical ly recon gurable designs starting from behavior level speci cations for a class of dsp applications. An Integer Linear Programming (ilp) model is ...

This article addresses the ubiquitous topic of quality of service (QoS) aware connection provisioning in wavelength-routed WDM optical networks. The impact of the connection setup time of an optical connection has not been ...

In the state-of-the-art field-programmable gate arrays (FPGAs), logic circuits are synthesized and mapped on clusters of look-up tables. However, arithmetic operations benefit from an existing dedicated adder along with a ...

This paper presents an integrated design system called SPARCS (Synthesis and Partitioning for Adaptive Reconfigurable Computing Systems) for automatically partitioning and synthesizing designs for reconfigurable boards ...

Optimizing area and timing have long been considered to be the main design challenges in high-level synthesis. A lot of research has been conducted in this area and many techniques to improve performance have been suggested. ...

One of the major enhancements that can be made to the high-level synthesis (HLS) process is reducing the overall area of a design in order to either decrease the manufacturing costs or to introduce more functionality to ...

This paper proposes a Unified Specification Model (USM) of concurrency and coordination compatible with VHDL. The specification model embodies a uniform treatment of computation, communication channels, and memories, ...