This paper presents a step down, switched mode power converter for use in multi-standard envelope tracking radio frequency power amplifiers (RFPA). The converter is based on a programmable order sigma delta modulator that ...

This paper presents a simulated annealing algorithm in order to solve the nonpreemptive open-shop scheduling problem with the objective of minimizing the makespan. The method is based on a simulated annealing algorithm ...

This paper presents a switching DC-DC Buck converter with enhanced light-load efficiency for use in noise-sensitive applications. Low noise, spur free operation is achieved by using a sigma-delta-modulator (ΣΔ) based ...

System-on-chip (SOCs) test minimization has received a lot of attention in the past few years. However, most recent work assumed flat hierarchy. This assumption is unrealistic especially in the case of non-mergeable legacy ...

Network-on-Chip (NoC) is an on-chip communication methodology that has been proposed as an alternative to bus-based communication in order to cope with the increased complexity in embedded designs. This paper presents a ...

System-On-Chip (SOCs) test minimization is an important problem that has been receiving considerable attention. The problem is tightly coupled with the number of TAM bits, power, and wrapper design. This paper presents a ...

This paper presents an efficient method to determine minimum SOC test schedules based on simulated annealing. The problem is solved using a partitioned testing scheme with run to completion that minimizes the number of ...

This paper presents a model for option pricing in markets that experience financial crashes. The stochastic differential equation (SDE) of stock price dynamics is coupled to a post-crash market index. The resultant SDE is ...

Parallel genetic algorithms techniques have been used in a variety of computer engineering and science areas. This paper presents a parallel genetic algorithm to solve the site layout problem with unequal-size and constrained ...