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Browsing by Author "Harmanani, H."

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Browsing by Author "Harmanani, H."

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  • An evolutionary algorithm for solving the geometrically constrained site layout problem 
    Zouein, P.; Harmanani, H.; Hajar, A. (ASCE, 2017-05-10)
    Construction site layout has been recognized as an important activity in construction site planning by field practitioners and researchers alike. This problem involves coordinating the use of limited space to accommodate ...
  • Genetic Algorithm for Solving Site Layout Problem with Unequal-Size and Constrained Facilities 
    Zouein, P. P.; Harmanani, H.; Hajar, A. (2017-04-11)
    This paper presents an investigation of the applicability of a genetic approach for solving the construction site layout problem. This problem involves coordinating the use of limited site space to accommodate temporary ...
  • A genetic algorithm for testable data path synthesis 
    Harmanani, H.; Saliba, R.; Khoury, M. (IEEE, 2017-03-30)
    A high level synthesis for testability method is presented with the objective to generate testable resistor transistor logic designs from behavioral descriptions. The approach is formulated as an allocation problem and ...
  • A hybrid distributed test generation method using deterministic and genetic algorithms 
    Harmanani, H.; Karablieh, B. (IEEE, 2017-03-30)
    Test generation is a highly complex and time-consuming task. In this work, we present a distributed method for combinational test generation. The method is based on a hybrid approach that combines both deterministic and ...
  • A hybrid heuristic approach to optimize rule-based software quality estimation models 
    Azar, D.; Harmanani, H.; Korkmaz, R. (2016-03-24)
    Software quality is defined as the degree to which a software component or system meets specified requirements and specifications. Assessing software quality in the early stages of design and development is crucial as it ...
  • An incremental approach for test scheduling and synthesis using genetic algorithms 
    Harmanani, H.; Hajar, A. (IEEE, 2017-03-28)
    This paper presents a new and an efficient method for concurrent BIST synthesis and test scheduling. This method maximizes concurrent testing of modules while performing the allocation of functional units, test registers, ...
  • A method for data path synthesis using neural networks 
    Harmanani, H. (IEEE, 2017-04-03)
    Presents a deterministic parallel algorithm to solve the data path allocation problem in high-level synthesis. The method is based on the modified Hopfield neural network model of computation and the McCulloch-Pitts binary ...
  • A method for redesign for testability at the RT level 
    Harmanani, H.; Harfoush, S. (IEEE, 2017-03-30)
    A new method of redesign for testability at the register-transfer level (RTL) is proposed. The method identifies hard to test parts of a an RTL design synthesized either manually or automatically using high-level synthesis ...
  • A parallel genetic algorithm for the geometrically constrained site layout problem 
    Zouein, P.; Harmanani, H.; Hajar, A. (2018-10-15)
    Parallel genetic algorithms techniques have been used in a variety of computer engineering and science areas. This paper presents a parallel genetic algorithm to solve the geometrically constrained site layout problem that ...
  • Predicting stability of classes in an object-oriented system 
    Azar, D.; Harmanani, H.; Korkmaz, R. (2016-04-12)
    The stability of a class in object-oriented system is one software quality characteristic that is important to assess at the early development stages. However, a direct measure of this software quality characteristic is ...
  • SYNTEST 
    Harmanani, H.; Papchristou, C.; Chiu, S. (IEEE, 2017-03-30)
    The article introduces a new high-level synthesis method for self-testable RTL designs. A basic feature of this method is a structural testability model which treats testability as a structural design style integrated in ...
  • SYNTEST 
    Harmanani, H.; Papachristou, C.; Chiu, S.; Nourani, M. (IEEE, 2017-04-03)
  • Test insertion at the RT level using functional test metrics 
    Harmanani, H.; Harfoush, S. (IEEE, 2017-03-30)
    A new method of redesign for testability at the Register-Transfer Level (RTL) is proposed. The method identifies hard to test parts of a an RTL design synthesized either manually or automatically using high-level synthesis ...